This invention relates to transferring data between systems having a plurality of clocks with a plurality of different frequencies.
Frequently, digital systems will require sub-apparatus which operate at different clock frequencies, and which receive control information from a common data bus. If the respective sub-apparatus captures the distributed control information using its respective clock, rather than a common bus clock, there is potential for error. That is, transferring digital data from one clock domain to another clock domain is subject to metastability.
Typically, known systems utilize buffer memory and/or condition the phase of the clock in one or both of the clock domains to avoid the metastability. An example of this approach is described in U.S. Pat. No. 5,548,620. In this exemplary system, at respective clock domain interfaces, data is clocked through a master and a slave flip-flop at the output of the first domain and a master and a slave flip-flop at the input of the second domain. The master flip-flop of the first domain is clocked by the first domain clock. The slave flip-flop in the second domain is clocked by the second domain clock. The slave flip-flop in the first domain and the master flip-flop in the second domain are both clocked by respectively different clocks that are generated in phase locked loop circuitry.
Using this approach to the interfacing of data between clock domains can become complicated and expensive if multiple clock domains are involved. Thus there is a need for a simple approach to data interfacing to avoid metastability in digital apparatus having multiple clock domains.
The present invention is directed to clock domain interface circuitry for providing data interfacing between clock domains. This circuitry includes a first latch at the output of a first clock domain, and a second latch at the input to the second clock domain. The first and second latches are clocked by their respective domain clocks. An Enable Signal, which is a logical function of the respective clocks is applied to enable one of the first and second latches.